The invention relates to a differential amplifier circuit for regenerating complementary analog signals of a low amplitude, which includes a differential pair of field effect transistors whose common sources are connected to a first supply voltage via a load, a pair of loads which are connected to the drain of each transistor of the differential pair and to a second supply voltage, respectively, and a level regenerating circuit, having a diode for deriving the signals from the drain of one transistor of the differential pair.
This type of circuit is used for regenerating complementary analog signals having a low amplitude and a variable mean d.c. value for static memories with a medium and high integration density in integrated circuit technology based on gallium arsenide (GaAs).
A differential amplifier circuit of this kind is shown from European patent application No. 0,154,501. This document describes a differential amplifier circuit which comprises a differential pair of field effect transistors whose coupled sources are connected to a dc potential via a current source. The drains of the transistors of the differential pair are connected to a second d.c. supply voltage via a pair of loads. Each drain is also connected to the other drain via a diode. the objects of this known circuit are to reduce the instability of the low level, to increase the gain, and to maintain a low power consumption and a fast response.
However, such a circuit is not suitable for supplying output signals whose mean level is fixed, regardless of the input signals. Moreover, the output signals are highly dependent on capacitive loads. Therefore, such a circuit is essentially connected to a second differential circuit.
However, for the intended application in static memories, the output signals of such a differential amplifier must be strictly complementary, calibrated as regards amplitude and above all as regards absolute value as well as switching time, and must also be directly compatible with the so-called DCFL logic (Direct Coupled FET Logic). This means not only that the difference between the high level and the low level on the output must be constant, regardless of the input levels, but also that the mean value of this difference must have a fixed level, regardless of the level of the mean value of the difference between the input levels. Actually, in the memories the mean value of the difference between the high levels and the low levels often "floats". Therefore, these signals cannot be used for later processing, because they lead to ambiguous situations. Moreover, a high gain must be realized, because the signals supplied by the memories often have a low amplitude. Finally, the intended circuit must be insensitive to capacitive loads.